- Kyle Chua
Intel Unveils Advancements in Transistor Scaling Technology
Updated: Dec 18, 2023
Intel's latest breakthrough would likely help satisfy the ever-growing demand for greater computing power.
The semiconductor giant at International Electron Devices Meeting (IEDM) unveiled advancements in 3D stacked CMOS (complementary metal oxide semiconductor) transistors combined with backside power and direct backside contacts. These advancements maintain a pipeline of innovations for the company’s future process roadmap, underscoring the persistent evolution of Moore’s Law.
For those unfamiliar, Moore's Law is the observation that the number of transistors on a microchip doubles every two years. That means the speeds and capabilities of computers are always seeing an expontential increase, though their almost stay the same or are even lower than before.
"As we enter the Angstrom Era and look beyond five nodes in four years, continued innovation is more critical than ever," said Sanjay Natarajan, Intel Senior Vice President and General Manager of Components Research.
"At IEDM 2023, Intel showcases its progress with research advancements that fuel Moore’s Law, underscoring our ability to bring leading-edge technologies that enable further scaling and efficient power delivery for the next generation of mobile computing."
Intel said its researchers have identified key areas necessary to continue scaling by efficiently stacking transistors. The research it unveiled at the event shows the ability to vertically stack complementary field effect transistors (CFET) at a scaled gate pitch down to 60nm, which is an industry first. This allows area efficiency and performance benefits by stacking transistors.
It is also combined with backside power and direct backside contacts. In line with this, Intel is working to have PowerVia, its own backside power delivery technology, manufacturing-ready by 2024. Backside power delivery essentially moves all the power-delivering interconnects that power transistors to underneath the silicon, allowing them to be larger and less resistive.
Looking to the future, Intel said it's working to furhter innovate the incorporation of more transistors on silicon to enhance performance. The semiconductor giant's researchers hope to have up to a trillion transistors on a package by 2030. Such an innovation is centred on recent advamcenets in backside power delivery and the application of 2D channel materials.
"Transistor scaling and backside power are key to helping meet the exponentially increasing demand for more powerful computing," Intel wrote in a news release. "Year after year, Intel meets this computing demand, demonstrating that its innovations will continue to fuel the semiconductor industry and remain the cornerstone of Moore’s Law."
Intel unveiled advancements in 3D stacked CMOS (complementary metal oxide semiconductor) transistors combined with backside power and direct backside contacts.
The semiconductor giant's research shows the ability to vertically stack complementary field effect transistors (CFET) at a scaled gate pitch down to 60nm, which is an industry first.
This allows area efficiency and performance benefits by stacking transistors.